Electronic devices such as computers are often interconnected to peripheral devices (e.g., input/output (I/O) devices, memory devices, printers). A Universal Serial Bus (USB) is often used to communicate data between a host processor of an electronic device and peripheral devices.
A USB host controller manages the transfer of data over the USB. A Host Control Interface (HCI) is a register level interface that allows for USB hardware to communicate with a host controller driver of an electronic device. Enhanced Host Controller Interface (EHCI) is a high speed USB host controller standard. The EHCI provides support for two categories of data transfer types: periodic and asynchronous.
Asynchronous data transfers typically involve the transfer of large amounts of data at variable times using any available bandwidth; however bandwidth and latency limits are not guaranteed. Asynchronous data transfers are typically not time sensitive, but must be delivered (in contrast to periodic data transfers, such as isochronous data transfers, that are time sensitive but do not necessarily need to be delivered). Asynchronous data transfers involve accessing an asynchronous schedule stored in main memory, which is a circular linked list of schedule work items used to provide round-robin service opportunity for asynchronous data transfers.
Power management of electronic devices is becoming more of a concern due to the implementation of battery powered mobile system platforms. While a USB is quite effective at moving large amounts of data very quickly, current implementations of USB host controllers are relatively inefficient with respect to power consumption.
When the asynchronous schedule is empty, the EHCI standard calls for a 10 μs sleep mode to avoid unnecessarily occupying too much memory bandwidth. This solution does not address the power implication of continually spinning through the asynchronous schedule in system memory, and occasionally pausing for a period of 10 μs before resuming regular operation. This behavior may prevent the processor of an electronic device from entering a deeper sleep state. For example, a processor sleep state may have an associated “exit latency” (i.e., a time value indicating how long it takes for processor to exit the respective sleep state). Scheduled accesses to the asynchronous schedule every 10 μs would not permit the processor to enter a sleep state if the associated exit latency is greater than 10 μs. Thus, the current EHCI standard may cause the processor along with its memory sub-system to burn significant power at the system level.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as a discussion of other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.